Anti-Tamper Digital Clocks - An Overview

Anti-Tamper Digital Clocks - An Overview

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means for analyzing that takes advantage of the plurality of delayed monotone alerts to detect a voltage fault and

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Another element of the invention may well reside in an equipment for detecting voltage tampering, comprising a circuit that provides a monotone sign, a plurality of resettable hold off line segments, and an Appraise circuit: The circuit supplies a monotone signal throughout an Appraise time frame. The plurality of resettable delay line segments hold off the monotone signal to make a respective plurality of delayed monotone alerts.

an Assess circuit, induced by the clock, that utilizes the plurality of delayed monotone alerts to detect a clock fault.

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eleven. The equipment for detecting clock tampering as defined in claim 8, wherein-the means for assessing decides whether the quantity of types in the plurality of delayed monotone signals differs from a h2o stage range by greater than a predetermined threshold.

Another aspect of the creation may reside in an apparatus for detecting clock tampering, comprising: signifies 250 for delivering a monotone sign 220 all through a clock Examine period of time 310 PROENC linked to a clock CLK; indicates 210 for delaying the monotone sign employing a plurality of resettable delay line segments to crank out a respective plurality of delayed monotone alerts 230 obtaining discretely growing hold off moments in between a minimum amount hold off time and also a optimum delay time; and implies 240 for utilizing the clock CLK to trigger an Assess circuit 240 that takes advantage of the plurality of delayed monotone signals to detect a clock fault.

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